1. Field of the Invention
The present invention relates to a current mirror circuit, or a current driving circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, a current mirror circuit is employed in order to duplicate an electric current that flows through a given path. FIG. 1 is a circuit diagram which shows a configuration of a typical cascode current mirror circuit.
A current mirror circuit 200 duplicates an input current Iin that passes through an input terminal P1 so as to generate an output current Iout, and outputs the output current Iout thus generated via an output terminal P2. The current mirror circuit 200 includes a first transistor M1 through a fourth transistor M4, each of which is configured as a P-channel MOSFET, and a resistor R1. The first transistor M1, the second transistor M2, and the resistor R1 are connected in series in this order on a path for the input current Iin, i.e., between a power supply terminal P3 and the input terminal P1. The third transistor M3 and the fourth transistor M4 are connected in series in this order on a path for the output current Iout, i.e., between the power supply terminal P3 and the output terminal P2. The gate of the second transistor M2 and the gate of the fourth transistor M4 are both connected to the input terminal P1. Furthermore, the gate of the first transistor M1 and the gate of the third transistor M3 are both connected to the drain of the second transistor M2.
In order for an accurate proportional relation to be satisfied between the output current Iout and the input current Iin in the current mirror circuit 200 shown in FIG. 1, a relation in which the drain-source voltage VdsM1 of the first transistor M1 is equal to the drain-source voltage VdsM3 of the third transistor M3 must be satisfied.
The gate-source voltages of the first transistor M1, the second transistor M2, and the fourth transistor M4 will be represented by the symbols Vth1, Vth2, and Vth4, respectively. In this case, the gate voltages VA of the first transistor M1 and the third transistor M3 are each represented by the following Expression (1).VA=Vcc−Vth1  (1)
Furthermore, the gate voltages VB of the second transistor M2 and the fourth transistor M4 are each represented by the following Expression (2).VB=Vcc−Vth1−ΔV  (2)
Here, ΔV=R1×Iin.
In this case, the drain voltage VC of the first transistor M1 and the drain voltage VD of the third transistor M3 are represented by the following Expressions (3) and (4), respectively.VC=VB+Vth3=Vcc−Vth1+Vth3−ΔV  (3)VD=VB+Vth4=Vcc−Vth1+Vth4−ΔV  (4)
When the gate-source voltages Vth1 through Vth4 of all the transistors M1 through M4 are the same, the drain voltage VC of the first transistor M1 and the drain voltage VD of the third transistor M3 are each equal to (Vcc−ΔV). That is to say, the drain-source voltage VdsM1 of the first transistor M1 and the drain-source voltage VdsM3 of the third transistor m3 are each equal to ΔV. Thus, such an arrangement is capable of duplicating the input current Iin according to a predetermined mirror ratio.
However, when the input current Iin is small, the voltage drop ΔV that occurs at the resistor R1, i.e., the drain-source voltage of each of the first transistor M1 and the third transistor M3, becomes small. This leads to the mirror ratio deviating from its design value, resulting in a problem in that the output current Iout cannot be accurately generated.
Conversely, when the input current Iin is large, the voltage drop ΔV that occurs at the resistor R1 becomes large, leading to a reduction in the electric potential VB at the input terminal P1. As a result, the voltage between both terminals of a current source 202 configured to generate the input current Iin becomes small, leading to a problem in that the current source 202 cannot generate the input current Iin that should be supplied.